Cypress Semiconductor /psoc63 /PDM0 /CTL

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Interpret as CTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PGA_R0PGA_L0 (SOFT_MUTE)SOFT_MUTE 0 (STEP_SEL)STEP_SEL 0 (ENABLED)ENABLED

Description

Control

Fields

PGA_R

Right channel PGA gain: +1.5dB/step, -12dB ~ +10.5dB ‘0’: -12 dB ‘1’: -10.5 dB … ‘15’ +10.5 dB (Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_R)

PGA_L

Left channel PGA gain: +1.5dB/step, -12dB ~ +10.5dB ‘0’: -12 dB ‘1’: -10.5 dB … ‘15’: +10.5 dB (Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_L)

SOFT_MUTE

Soft mute function to mute the volume smoothly ‘0’: Disabled. ‘1’: Enabled. (Note: This bit is connected to AR36U12.PDM_CORE_CFG.SOFT_MUTE)

STEP_SEL

Set fine gain step for smooth PGA or Soft-Mute attenuation transition. ‘0’: 0.13dB ‘1’: 0.26dB (Note: This bit is connected to AR36U12.PDM_CORE2_CFG.SEL_STEP)

ENABLED

Enables the PDM component: ‘0’: Disabled. ‘1’: Enabled.

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